Dynamic Random Access Memory (DRAM) memory systems may require refresh operations to be implemented on a regular basis. Existing practice is to specify a fixed refresh period (e.g., 64 msec) and DRAM memory systems are built to conform to the fixed refresh period. Variation in the refresh needs of individual memory cells in a DRAM memory system necessitates that the weakest memory cell (i.e., the one requiring the most frequent refresh) determines the refresh requirement for the entire DRAM. Refresh requirements for cells in a DRAM memory system will form a distribution, and the distribution exhibits a fairly long tail of refresh requirements for quite frequent refreshes for a very small percentage of the cells. Since the refreshes are done on a per row basis (typically 8K bits per row), the weakest cell in a row will determine the refresh requirements of any given row, and therefore the row containing the weakest cell will determine the refresh period needed by all of the rows in the DRAM. Thus, many rows in a DRAM memory system are being refreshed more frequently than required, which wastes system resources.